1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a multi-bank semiconductor memory device with a plurality of banks. More specifically, the present invention relates to a multi-bank synchronous semiconductor memory device in which an instruction of a mode of operation is applied in the form of a command in synchronization with a clock signal.
2. Description of the Background Art
In recent years, synchronous semiconductor memory devices which input and output data in synchronization with an external clock signal such as a system clock have been more and more widely used to transmit data at high speed and reduce the difference between the processing speed of processor and that of memory.
FIG. 39 is a timing chart representing an operation in reading data of a conventional synchronous semiconductor memory device. Referring to FIG. 39, a data read operation in the conventional synchronous semiconductor memory device will now be described. In the synchronous semiconductor memory device, a mode of operation is instructed in the form of a command. A command is provided by a combination of the logic states of external control signals and in some modes an address signal bit at a rising edge or the like of a clock signal CLK.
In FIG. 39, at the rising edge of clock signal CLK in clock cycle #0, a chip select signal /CS and a row address strobe signal /RAS are each set to a low level and a column address strobe signal /CAS and a write enable signal /WE are each set to a high level. This combination of the states is referred to as "an active command" and designates activating an array. Activation of an array indicates the state in which a series of operations are completed from the selection of a word line in a memory cell array to the sensing, amplification and latching by sense amplifiers of the data of memory cells connected to the selected word line. When the active command is applied, a row select operation is internally performed using an address signal applied when the command is applied as a row address signal, the word line corresponding to the addressed row is selected and the data of a selected memory cell is sensed, amplified and latched.
When a so-called RAS-CAS delay time in a standard DRAM elapses, a column select operation is enabled. In FIG. 39, at the rising edge of clock signal CLK in clock cycle #2, chip select signal /CS and column address strobe signal /CAS are each set to a low level and row address strobe signal /RAS and write enable signal /WE are each set to a high level. This state is referred to as a read command and designates reading data. When the read command is applied, a column select operation is performed using an address signal AD applied when the command is applied as a column address signal Y to read the data of a memory cell on the selected column. Synchronous semiconductor memory devices have a period referred to as "CAS latency" which determines the period from application of a read command until valid data is defined. FIG. 39 shows an example with a CAS latency of 2. Thus, the first read data Q0 is defined at the rising edge of clock signal CLK in clock cycle #4.
Internally, an address generator referred to as a burst address counter uses the address applied when the read command is applied as the head address, to change a column address in a predetermined sequence for each cycle and a column select operation is performed. Thus, data Q1, Q2 and Q3 are output in clock cycles #5, #6 and #7. The number of data which can be successively read when one read command is applied is referred to as a burst length. FIG. 39 represents a data read operation for a burst length of four.
At the rising edge of clock signal CLK in clock cycle #7, chip select signal /CS, row address strobe signal /RAS and write enable signal /WE are each set to a low level and column address strobe signal /CAS is set to a high level. This state combination is referred to as a precharge command and the array is driven from an active state to an inactive state. Thus, a word line in a selected state is driven to a non-selected state, a sense amplifier which has latched the data of a memory cell is inactivated, and a bit line of each column is returned to a predetermined precharge potential.
The precharge command cannot be applied at a timing faster than the clock cycle for reading the last burst-length data by the cycle(s) of the CAS latency or greater, since the array is inactivated before data is read from a memory cell. However, an internal data read circuit can transfer burst-length data even when the array returns to a precharge state (i.e., the internal read circuit operates independently of row-related circuitry and successively transfers burst-length data).
Since a mode of operation is designated by a combination of the states of external signals at a rising edge of clock signal CLK and data is input or output in synchronization with a clock signal, the timing of an internal operation can be determined without taking the skew of each control signal into consideration and thus the internal operation can be started at an earlier timing and hence fast access can be achieved. Furthermore, since output data is made definite in synchronization with clock signal CLK, an external device can sample data at a rising edge of clock signal CLK and data can be read and written at the same rate as that of clock signal CLK and hence fast data transfer is accomplished.
FIG. 40 is a timing chart representing an operation in writing data of a conventional synchronous semiconductor memory device. Referring to FIG. 40, the data write operation will now be described. In FIG. 40, an active command is applied in clock cycle #0 and the array is driven to an active state.
Then, in clock cycle #2 at the rising edge of clock signal CLK, chip select signal /CS, column address strobe signal /CAS and write enable signal /WE are each set to a low level and row address strobe signal /RAS is set to a high level. This state combination is referred to as a write command and designates writing data. When a write command is applied, an operation for selecting a column of memory cells is performed using an address signal AD applied when the write command is applied as a column address signal. In writing data, data to be written is provided simultaneously with the write command and data D0 provided in clock cycle #2 is taken into the synchronous semiconductor memory device. Thereafter, written data D1, D2 and D3 are successively written in clock cycles #3, #4 and #5, respectively. In writing data also, the burst address generator internally operates to generate burst addresses for successive column select operations and write data D0-D3 are internally written successively into selected columns of memory cells in a predetermined sequence.
When writing data operation is completed, a precharge command is applied at the rising edge of the clock signal CLK in clock cycle #6 and the array is driven to an inactive state. In writing data also, a precharge command cannot be applied until the period corresponding to the CAS latency in reading data elapses after the writing of burst-length data is completed. In writing data also, the number of data which can be successively written with one write command is referred to as a burst length. More specifically, burst length represents the number of data which can be successively accessed when an access command for designating writing/reading data, e.g., write command or read command, is applied.
In writing data also, data to be written is taken into the semiconductor memory device in synchronization with the clock signal. Thus, data can be written at the same rate as clock signal CLK and fast writing can thus be achieved.
As described above, a synchronous semiconductor memory device takes external signals and outputs read data in synchronization with a clock signal and thus allows fast data transfer. However, to switch pages (i.e., to select another word line) in a synchronous semiconductor memory device with only one array, such a sequence is needed that a precharge command is once applied in order to inactivate the array and then again an active command is applied in order to drive a new page (a word line) to a selected state. Accordingly, the page switching period prevents data transfer and hence fast access. In order to avoid access interruption in switching pages and the like, the synchronous semiconductor memory device is configured into a plurality of banks which can be driven to an active state/inactive state independently of each other and successively activated and inactivated in a predetermined sequence so that the precharge time can be externally concealed and fast access can be achieved.
An operation of a synchronous semiconductor memory device of the bank configuration will now be described. FIG. 41 schematically shows the entire configuration of a synchronous semiconductor memory device including a plurality of banks BK0-BKn. Bank control circuits BCT0-BCTn are provided for banks BL0-BKn, respectively. Bank control circuits BCT0-BCTn receive a bank address signal BA from a bank address buffer BAB and an operation mode designating signal from a control input buffer CIB which in turn receives control signal /CS, /WE, /CAS and /RAS. Banks BK0-BKn are commonly coupled with an input/output circuit IOB.
Each of bank control circuits BCT0-BCTn is activated when a bank address signal from bank address buffer BAB specifies a corresponding bank, to control the operation of the corresponding bank in response to an operation mode designating signal output from control input buffer CAB. Since the activation/inactivation of bank control circuits BCT0-BCTn is designated by bank address signal from bank address buffer BAB, bank control circuits BCT0-BCTn can independently drive the respective banks BK0-BKn to active/inactive state. Note that banks BK0-BKn each have a plurality of memory cells arranged in a matrix.
One example of the operation sequence of the semiconductor memory device with a plurality of banks shown in FIG. 41 will now be described with reference to FIG. 42. FIG. 42 represents an operation in reading data for a burst length of four and CAS latency of four. An active command is applied in clock cycle #0, and bank activating operation is performed in response to a bank address signal of address signal AD (not shown in FIG. 41). Bank address signal BA applied simultaneously with the active command designates bank BK0, and bank control circuit BCT0 activates bank BK0.
A read command is applied in clock cycle #2, and using an address applied when the read command is applied as a column address signal (Y), a column select operation is performed. Bank address signal BA designates bank BK0, and bank control circuit BCT0 selects and connects a corresponding memory cell of bank BK0 to input/output circuit IOB to transmit the data of the selected memory cell in bank BK0 to input/output circuit IOB. Since the CAS latency is two, the data read from bank BK0 is defined at the rising edge of clock signal CLK in clock cycle #4. Since the burst length is four, data Q0, Q1, Q2 and Q3 are successively read from bank BK0.
In clock cycle #4, an active command is again applied and bank address BA designates bank BK1. Bank control circuit BCT1 is activated which activates bank BK1 according to the active command from control input buffer CIB.
At the rising edge of clock signal CLK in clock cycle #6, a read command is applied together with a bank address which in turn designates bank BK1. Bank control circuit BCT1 is activated, a memory cell in bank BK1 is selected and the data of the selected memory cell is read. The data from bank BK1 is defined after two clock cycles. Accordingly, after data Q3 from bank BK0 is read in clock cycle #7 in successively reading the burst-length data from bank BK0, data Q0 . . . from bank BK1 are successively read starting at clock cycle #8.
While the data are read, a precharge command is applied in clock cycle #7. Together with the precharge command, a bank address for designating bank BK0 is applied to designate precharging the bank BK0 and bank BK0 is then inactivated under the control of bank control circuit BCT0. An active command is then applied in clock cycle #8, and bank address BA applied when the active command is applied designates bank BK2.
At the rising edge of clock signal CLK in clock cycle #12, a read command is applied together with bank address BA which in turn designates bank BK2. Thus, after data Q3 from bank BK1 is read in clock cycle #11, the data from the bank BK2 are read successively.
Since a plurality of banks are activated/inactivated in a predetermined order, as shown in FIG. 42, data can be read while concealing the time for precharging the banks and fast reading can thus be achieved. The sequence of successively activating the banks in a predetermined sequence and selecting memory cells writing data. Since the banks are successively activated and write commands are applied, writing data in switching pages can be done by switching the banks and thus data can be written successively.
The operation will now be described for successively precharging eight banks BK0-BK7 as banks BK0-BKn while writing data into one bank BK0 under a condition of a burst length of eight, a CAS latency of three and a RAS precharge cycle of three clock cycles. Here, the RAS precharge cycle is a period required till activating a bank after a precharge command is applied to the bank.
Referring to FIG. 43, an active command is applied in clock cycle #1 and bank BK0 is activated.
In clock cycle #4, a write command is applied to designate writing data into bank BK0, and the data D0 provided in clock cycle #4 is written into bank BK0. Thereafter, written data D1-D7 provided in clock cycles #5-#11 are successively written into bank BK0.
Meanwhile, precharge commands are applied from clock cycle #5 through clock cycle #11 while changing a bank address for each clock cycle to successively designate banks BK1-BK7 so that banks BK1-BK7 are precharged successively.
In clock cycle #11, writing data into bank BK0 is completed and a precharge command is applied to bank BK7. Again, all the control signals are once set to high level and an NOP (no operation) command is set. Thus, any new operation is not designated in the synchronous semiconductor memory device.
In clock cycle #13, a precharge command is applied for bank BK0. Writing all the data in bank BK0 is completed and then bank BK0 is precharged. With the RAS precharge clock cycle of three, an active command for bank BK7 can be applied in clock cycle #14 and bank BK7 can thus be activated. Then, an active command for bank BK0 is applied in clock cycle #17. This operation is repeated thereafter.
For the operation sequence shown in FIG. 43, a data write mask command (a write word mask command) DQM is in a low-level inactive state and data to be written cannot be masked. In other words, supplied data to be written D0-D7 are all written into bank BK0. However, when a precharge command and a bank address are used to return one bank to a precharge state in each clock cycle, a long period of time is disadvantageously required for inactivating all of the banks.
FIG. 44 represents another operation sequence in writing data. The figure also represents the operation in which bank BK0 has data of a burst length of eight written thereinto while the other banks are successively precharged. In FIG. 44, write word mask commands are applied in clock cycles #7 and #10 with signal DQM set to high level and thus writing for the data words is prohibited in these clock cycles. The write word mask command, which is an external signal, is a type of command, and inputting two commands simultaneously in the same cycle is prohibited to reduce the load on an external controller. Thus, when write word mask command DQM is set to an active state, external control signals /CS, /RAS, /CAS and /WE are set to NOP command state. In this state a processing for merely masking writing data is performed.
More specifically, a precharge command for a bank cannot be applied in clock cycles #7 and #10. Thus, in the operation sequence shown in FIG. 44, bank BK7 receives a precharge command in clock cycle #13 and is thus precharged. Precharging the bank BK0 is designated in the next clock cycle #14. Since the RAS precharge cycle is three clock cycles, an active command for bank BK7 can be applied in clock cycle #16 and an active command for bank BK0 can be applied in the next clock cycle #17.
Thus, when the write word masking is used in a clock cycle, commands such as active command and precharge command cannot be input in that clock cycle. Thus, it is not allowed to apply active and precharge commands successively to other banks for successively activating/inactivating the banks in an interleaving manner to achieve fast access.
In reading data also, command DQM instructs read word masking, and a similar problem arises.
The synchronous semiconductor memory device supports an all-bank precharge command for precharging all banks simultaneously. FIG. 45 represents the all-bank precharge command. More specifically, the all-bank precharge command is applied by setting chip select signal /CS, row address strobe signal /RAS and write enable signal /WE to low level and column address strobe signal /CAS and a particular address signal bit Ad10 to high level at a rising edge of clock signal CLK. In this state, precharging all the banks is designated. When address bit Ad10 is set to low level, a single-bank precharge command is applied to precharge the bank specified by the current bank address.
The use of such an all-bank precharge command allows all banks to be precharged simultaneously. However, when all banks are precharged simultaneously, the banks have to be successively activated by active commands and such generation sequence adversely affects the advantage of the bank configuration that banks can be activated/inactivated in an interleaving manner for writing/reading data to achieve fast data transfer.
Furthermore, if the number of banks is increased, these banks are successively activated/inactivated is write/read data. However, synchronous semiconductor memory devices have the conditions referred to as CAS latency and burst length for reading data and also have RAS precharge cycle and RAS-CAS delay cycle (i.e., the time required from application of an active command until the first application of a read/write command) corresponding to the RAS/CAS delay time of the standard DRAMs. Thus, the control for periodically activating/inactivating a number of banks while satisfying the conditions is extremely complicated, and thus each bank cannot be readily accessed in an interleaving manner.
In particular, is a case in which the number of banks is increased, when active, read/write and precharge commands are periodically applied to access each bank in a predetermined sequence, and if active, read/write and precharge commands are applied in each clock cycle, and a periodic command application sequence is to be implemented, a plurality of commands may have to be applied in one clock cycle depending on the conditions of CAS latency, burst length, RAS precharge cycle and RAS-CAS delay cycle. The regularity in the command application sequence is deteriorated and hence the continuity in data access control, and thus fast data transfer cannot be achieved.
Such synchronous semiconductor memory devices are subject to various tests in the manufacturing process in order to ensure their reliability. Such tests require writing/reading data in order to determine whether data is read/written accurately. However, if the number of banks is increased, the control for successively activating banks in a predetermined sequence and in an interleaving manner to read/write data becomes complicated, as described above, and thus data cannot be read/written at high speed. In particular, testing requires reading/writing data from/into all of the memory cells in a semiconductor memory device. Accordingly, if the interleaving of the respective banks as described above cannot readily be achieved, data cannot be read/written fast and testing time is disadvantageously increased.
Furthermore, in precharging banks with the all-bank precharge command, all banks must be in a prechargeable state and the timing of application of the all-bank precharge command is limited to a timing prior to reading the last data in successive data and the like. Thus, it is difficult to use the all-bank precharge command to achieve successive access.
Furthermore, a memory cell select command, such as active command and read/write command, is used together with a bank address signal specifying a bank in which a memory cell is selected and a memory cell select operation is performed in the specified bank. Accordingly, a plurality of banks cannot be accessed simultaneously and are thus inconvenient for some content of the processing.